1. Field of the Invention
The present invention generally relates to power management, and more particularly to a system and method of dynamically switching the threshold of a first-in first-out (FIFO) buffer.
2. Description of the Prior Art
Intel released the High Definition Audio (HDA) specification in 2004. The specification is documented in the Intel® High Definition Audio Specification, Revision 1.0 and subsequent revision(s) (http://www.intel.com/standards/hdaudio/), the disclosure of which is hereby incorporated by reference.
FIG. 1 illustrates a block diagram of the HDA architecture. A central processing unit (CPU) 10 is connected, via a host bus 11, to a memory controller 12, which controls the access of one or more system memories 13. The memory controller 12 is connected, via a system bus (such as Peripheral Component Interconnect or PCI) 14, to a HDA controller (“HDAC”) 15. The HDAC 15 is further connected to one or more coder/decoder (codec) 17 via a HDA link 16. The HDA controller 15 includes one or more direct memory access (DMA) engines or controllers (the “DMA”) 150, which control the stream data transportation between the system memory 13 and the codecs 17. The HDA link 16 facilitates the transportation of control signals and data between the HDAC 15 and the codecs 17. Each codec 17 includes one or more converters (“C”), which convert output digital signal into analog form to an output device (such as speaker), or convert received analog signal into digital form from an input device (such as microphone).
The DMA 150 has a queue, such as a first-in first-out buffer (“FIFO”) for maintaining the stream on the HDA link 16 by storing sufficient amount of data, such that no data under run or overrun occurs. Before sending out data to the HDA link 16, the HDAC 15 will issue a bus master cycle to request next stream data from the system memory 13 whenever the amount of the stream data in the FIFO is less than a threshold value. The FIFO threshold value and the burst length are associated with the FIFO size, as shown in Table 1, where h represents a hexadecimal number, and DW represents a double word (or 4-byte data).
TABLE 1FIFO sizeFIFO thresholdBurst length40h DW31h DW10h DW 30h DW21h DW10h DW 20h DW19h DW8h DW10h DW dh DW4h DW 8h DW 7h DW2h DW 4h DW 4h DW1h DWOthers 4h DW1h DW
The FIFO threshold value is utilized to make the HDAC 15 be aware of the time to issue a bus master cycle to retrieve data of the system memory 13 for playback or to send back data to the system memory 13 for recording. The FIFO threshold, accordingly, provides tolerance capability that prevents data under run or overrun.
FIG. 2 illustrates an exemplary FIFO which has a FIFO size of 192 bytes, and a threshold value of 128 bytes. Taking 48 kHz sample rate, 2 channels each having 16 bits (or 2 bytes) for example, each frame thus contains 4 bytes of data, wherein each frame is regarded as a “data unit of transportation.” Whenever the amount of stream data in the FIFO is less than 128 bytes (i.e., the threshold), the HDAC 15 will issue a bus mater cycle. As each frame is transported in an interval time of 20.83 micro second (μs) (=1/(48×103)), which is regarded as a “time unit of transportation,” the 128 bytes therefore can keep 32 frames (=128/4) of data for about 666 micro second (=32×20.83) without under run.
In the HDA system of FIG. 1, input/output devices such as speakers, headsets, modems or microphones are connected to the HDAC 15 via codecs 17. Data transportation takes place through the HDA link 16 according to some control signals. For example, a serial digital output signal (AZSDO) is used to send serial formatted data to the output device; a serial digital input signal (AZSDI) is used to receive serial formatted data from the input device; a synchronization signal (SYNC) driven by the HDAC 15 is used for frame synchronization and outbound tag signaling; a reset signal (AZRST#) is used to reset the HDA link 16; and a clock signal (AZBITCLK) provides 24 MHz clock source.
When a HDA driver requests the HDAC 15 and sets an associated RUN bit, the DMA 150 of the HDAC 15 then communicates with the codec 17 during playback, recording, command outbound ring buffer (CORB) sequence or response inbound ring buffer (RIRB) sequence.
The power management unit (PMU) 18 in FIG. 1 controls the power state Cx of the CPU 10. Hewlett-Packard, Intel and other companies co-developed an Advanced Configuration and Power Interface (ACPI) specification, which may be found at http://www.acpi.info/, the disclosure of which is hereby incorporated by reference. According to the ACPI, C0 power state is a state in which the system operates normally, and C1 through Cn power states are various sleeping states, where larger n indicates greater degree of idleness and power saving. The system may continue accessing the system memory 13 during C2 or below, while the system can no longer access the system memory 13 during C3 or above. In other words, whenever the CPU 10 is in C4 and the amount of data in the FIFO is less than the threshold, the CPU 10 requests data from the system memory 13 after changing from C4 to C2. Likewise, whenever the CPU 10 is in C3 and the amount of data in the FIFO is less than the threshold, the CPU 10 requests data from the system memory 13 after changing from C3 to C2.
The HDAC 15 and the codec 17 may request a master or interrupt event during Cx sleeping state without software triggering. In this situation, the codec 17 drives AZSDI pin to signal the HDAC 15 for master or interrupt request. The signal AZSDI can be latched by the PMU 18 as a power management event (PME) to make the CPU 10 out of Cx state.
FIG. 3 illustrates a flow diagram demonstrating how the HDA system enters and exits sleeping state. At the beginning, the PMU 18 issues a signal to force the CPU 10 into C3 or C4 state (step 30). Next, in step 31, the HDAC RUN bit is checked. If the RUN bit is inactive, the CPU 10 is in C3/C4 state (step 32A). Meanwhile, the HDA link 16 is in reset state (step 33A), which hides the codec 17 such that the HDA link 16 does not function. Subsequently, in step 34A, if the HDAC 15 detects active signal AZSDI, the CPU 10 will exit from C3/C4 into C0/C2 (step 35); otherwise, if the HDAC 15 detects inactive signal AZSDI, the CPU 10 will remain in C3/C4 (i.e., the step 32A).
If the RUN bit in the step 31 is active, the CPU 10 is in C3/C4 state (step 32B). Meanwhile, the HDA link 16 exits the reset state (step 33B), which uncovers the codec 17 such that the HDA link 16 can function. Subsequently, in step 34B, if the HDAC 15 detects active signal AZSDI or the amount of the FIFO is less than the threshold, the CPU 10 will exit from C3/C4 into C0/C2 (step 35); otherwise, the CPU 10 will remain in C3/C4 (i.e., the step 32B).
When the CPU 10 is in the C3/C4 state, the devices are apt to get bus master cycle. According, it is not necessary to prepare too much data in the FIFO buffer for playback or recording. Conventional HDA system, either in C3/C4 state or C0/C2 state, adapts fixed threshold value, which causes the CPU 10 to frequently exit from C3/C4 into C0/C2. For the reason that conventional HDA system could not effectively change between sleeping states to save power, a need has arisen to propose a novel control mechanism for saving more power to lengthen the operating time of a portable electronic device with limited power supply.